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| author | Umesh Nerlige Ramappa <[email protected]> | 2022-11-10 17:19:13 +0000 |
|---|---|---|
| committer | Rodrigo Vivi <[email protected]> | 2022-11-23 11:46:51 -0500 |
| commit | 264bc5d3ebc5d695339ff84d8635773c23e34ba9 (patch) | |
| tree | 25c05792e4fa1797f0bcff7ba48e11a9ff0dae11 /lib/memory-notifier-error-inject.c | |
| parent | 71b6b2557058d4374d11e792ec550a1a098fb7a9 (diff) | |
drm/i915/selftest: Bump up sample period for busy stats selftest
Engine busyness samples around a 10ms period is failing with busyness
ranging approx. from 87% to 115% as shown below. The expected range is
+/- 5% of the sample period. Fail 10% of the time.
rcs0: reported 11716042ns [91%] busyness while spinning [for 12805719ns]
When determining busyness of active engine, the GuC based engine
busyness implementation relies on a 64 bit timestamp register read. The
latency incurred by this register read causes the failure.
On DG1, when the test fails, the observed latencies range from 900us -
1.5ms.
Optimizing the 2x32 read by acquiring the lock and forcewake prior to
all reg reads reduces the rate of failure to around 2%, but does not
eliminate it.
In order to make the selftest more robust and always account for such
latencies, increase the sample period to 100 ms. This eliminates the
issue as seen in a 1000 runs.
v2: (Ashutosh)
- Add error to commit msg
- Include gitlab bug
- Update commit for inclusion of 2x32 optimized read
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4418
Signed-off-by: Umesh Nerlige Ramappa <[email protected]>
Acked-by: Tvrtko Ursulin <[email protected]>
Reviewed-by: Ashutosh Dixit <[email protected]>
Signed-off-by: John Harrison <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit 529d95a6067b74da9d4d5d9ab3009b35c98c5fce)
Signed-off-by: Rodrigo Vivi <[email protected]>
Diffstat (limited to 'lib/memory-notifier-error-inject.c')
0 files changed, 0 insertions, 0 deletions