clk: tegra: T114: add DFLL DVCO reset control

Add DFLL DVCO reset line control functions to the CAR IP block driver.

The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block.  This reset line is asserted upon SoC
reset.  Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP block will complete.

Thanks to Aleksandr Frid <[email protected]> for identifying this and
saving hours of debugging time.

Signed-off-by: Paul Walmsley <[email protected]>
Cc: Aleksandr Frid <[email protected]>
Cc: Peter De Schrijver <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>

0 files changed, 0 insertions, 0 deletions