arm64: fix midr range for Cortex-A57 erratum 832075

Register MIDR_EL1 is masked to get variant and revision fields, then
compared against midr_range_min and midr_range_max when checking
whether CPU is affected by any particular erratum. However, variant
and revision fields in MIDR_EL1 are separated by 16 bits, so the min
and max of midr range should be constructed accordingly, otherwise
the patch will not be applied when variant field is non-0.

Cc: [email protected] # 3.19+
Acked-by: Andre Przywara <[email protected]>
Reviewed-by: Paul Walmsley <[email protected]>
Signed-off-by: Bo Yan <[email protected]>
[will: use MIDR_VARIANT_SHIFT to construct upper bound]
Signed-off-by: Will Deacon <[email protected]>

0 files changed, 0 insertions, 0 deletions