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author | Changbin Du <changbin.du@intel.com> | 2017-08-18 17:49:58 +0800 |
---|---|---|
committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-09-18 15:22:16 -0700 |
commit | 7b4dc3c0da0d66e7b20a826c537d41bb73e4df54 (patch) | |
tree | 0bcb046d1addd6fc8c0c6f1b6e1c081ef6486ca4 /lib/flex_array.c | |
parent | 134dd2e616b9cd8300c08cd1b38987ded74f662f (diff) |
drm/i915/gvt: Fix incorrect PCI BARs reporting
Looking at our virtual PCI device, we can see surprising Region 4 and Region 5.
00:10.0 VGA compatible controller: Intel Corporation Sky Lake Integrated Graphics (rev 06) (prog-if 00 [VGA controller])
....
Region 0: Memory at 140000000 (64-bit, non-prefetchable) [size=16M]
Region 2: Memory at 180000000 (64-bit, prefetchable) [size=1G]
Region 4: Memory at <ignored> (32-bit, non-prefetchable)
Region 5: Memory at <ignored> (32-bit, non-prefetchable)
Expansion ROM at febd6000 [disabled] [size=2K]
The fact is that we only implemented BAR0 and BAR2. Surprising Region 4 and
Region 5 are shown because we report their size as 0xffffffff. They should
report size 0 instead.
BTW, the physical GPU has a PIO BAR. GVTg hasn't implemented PIO access, so
we ignored this BAR for vGPU device.
v2: fix BAR size value calculation.
Link: https://bugzilla.redhat.com/show_bug.cgi?id=1458032
Signed-off-by: Changbin Du <changbin.du@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
(cherry picked from commit f1751362d6357a90bc6e53176cec715ff2dbed74)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'lib/flex_array.c')
0 files changed, 0 insertions, 0 deletions