OMAP3: SDRC: Place SDRC AC timing and MR changes in CORE DVFS SRAM code behind Kconfig

The code that reprograms the SDRC memory controller during CORE DVFS,
mach-omap2/sram34xx.S:omap3_sram_configure_core_dpll(), does not
ensure that all L3 initiators are prevented from accessing the SDRAM
before modifying the SDRC AC timing and MR registers.  This can cause
memory to be corrupted or cause the SDRC to enter an unpredictable
state.  This patch places that code behind a Kconfig option,
CONFIG_OMAP3_SDRC_AC_TIMING for now, and adds a note explaining what
is going on.  Ideally the code can be added back in once supporting
code is present to ensure that other initiators aren't touching the
SDRAM.  At the very least, these registers should be reprogrammable
during kernel init to deal with buggy bootloaders.  Users who know
that all other system initiators will not be touching the SDRAM can
also re-enable this Kconfig option.

This is a modification of a patch originally written by Rajendra Nayak
<[email protected]> (the original is at http://patchwork.kernel.org/patch/51927/).
Rather than removing the code completely, this patch just comments it out.

Thanks to Benoît Cousson <[email protected]> and Christophe Sucur
<[email protected]> for explaining the technical basis for this and for
explaining what can be done to make this path work in future code.
Thanks to Richard Woodruff <[email protected]>, Nishanth Menon
<[email protected]>, and Olof Johansson <[email protected]> for their comments.

Signed-off-by: Paul Walmsley <[email protected]>
Cc: Rajendra Nayak <[email protected]>
Cc: Christophe Sucur <[email protected]>
Cc: Benoît Cousson <[email protected]>
Cc: Richard Woodruff <[email protected]>
Cc: Nishanth Menon <[email protected]>
Cc: Olof Johansson <[email protected]>

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