[Blackfin] arch: Prevent potential Core Hang situation

If the new value written to the PLL_CTL or VR_CTL register is the
same as the previous value, the PLL wake-up will occur immediately
(PLL is already locked), but the core and system clock will be
bypassed for the PLL_LOCKCNT duration. For this interval, code will
execute at the CLKIN rate instead of at the expected CCLK rate.
Software should guard against this condition by comparing the
current value to the new value before writing the new value.

Signed-off-by: Michael Hennerich <[email protected]>
Signed-off-by: Bryan Wu <[email protected]>

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