Merge patch series "Add basic ACPI support for RISC-V"

Sunil V L <sunilvl@ventanamicro.com> says:

This patch series enables the basic ACPI infrastructure for RISC-V.
Supporting external interrupt controllers is in progress and hence it is
tested using poll based HVC SBI console and RAM disk.

The first patch in this series is one of the patch from Jisheng's
series [1] which is not merged yet. This patch is required to support
ACPI since efi_init() which gets called before sbi_init() can enable
static branches and hits a panic.

Below are two ECRs approved by ASWG.
RINTC - https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
RHCT - https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view

Testing:
1) Build latest Qemu

2) Build EDK2 as per instructions in
https://github.com/vlsunil/riscv-uefi-edk2-docs/wiki/RISC-V-Qemu-Virt-support

3) Build Linux after enabling SBI HVC and SBI earlycon
CONFIG_RISCV_SBI_V01=y
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_HVC_RISCV_SBI=y

4) Build buildroot.

Run with below command.
qemu-system-riscv64   -nographic \
-drive file=Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1 \
-machine virt -smp 16 -m 2G \
-kernel arch/riscv/boot/Image \
-initrd buildroot/output/images/rootfs.cpio \
-append "root=/dev/ram ro console=hvc0 earlycon=sbi"

* b4-shazam-merge:
  RISC-V: Enable ACPI in defconfig
  RISC-V: time.c: Add ACPI support for time_init()
  clocksource/timer-riscv: Add ACPI support
  clocksource/timer-riscv: Refactor riscv_timer_init_dt()
  irqchip/riscv-intc: Add ACPI support
  RISC-V: cpu: Enable cpuinfo for ACPI systems
  RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()
  RISC-V: only iterate over possible CPUs in ISA string parser
  RISC-V: smpboot: Add ACPI support in setup_smp()
  RISC-V: smpboot: Create wrapper setup_smp()
  drivers/acpi: RISC-V: Add RHCT related code
  RISC-V: ACPI: Cache and retrieve the RINTC structure
  RISC-V: Add ACPI initialization in setup_arch()
  ACPI: processor_core: RISC-V: Enable mapping processor to the hartid
  RISC-V: Add support to build the ACPI core
  ACPI: OSL: Make should_use_kmap() 0 for RISC-V
  ACPI: tables: Print RINTC information when MADT is parsed
  crypto: hisilicon/qm: Fix to enable build with RISC-V clang
  platform/surface: Disable for RISC-V
  riscv: move sbi_init() earlier before jump_label_init()

Link: https://lore.kernel.org/r/20230515054928.2079268-1-sunilvl@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

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