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| author | Stephane Eranian <[email protected]> | 2014-05-15 17:56:44 +0200 |
|---|---|---|
| committer | Thomas Gleixner <[email protected]> | 2014-05-19 21:52:59 +0900 |
| commit | 722e76e60f2775c21b087ff12c5e678cf0ebcaaf (patch) | |
| tree | 55dba7d6ec8c33b7d40ed10c18f34459f16c5a2e /kernel/workqueue.c | |
| parent | 643fd0b9f5dc40fedbfbb908ebe6f1169284f7d8 (diff) | |
fix Haswell precise store data source encoding
This patch fixes a bug in precise_store_data_hsw() whereby
it would set the data source memory level to the wrong value.
As per the the SDM Vol 3b Table 18-41 (Layout of Data Linear
Address Information in PEBS Record), when status bit 0 is set
this is a L1 hit, otherwise this is a L1 miss.
This patch encodes the memory level according to the specification.
In V2, we added the filtering on the store events.
Only the following events produce L1 information:
* MEM_UOPS_RETIRED.STLB_MISS_STORES
* MEM_UOPS_RETIRED.LOCK_STORES
* MEM_UOPS_RETIRED.SPLIT_STORES
* MEM_UOPS_RETIRED.ALL_STORES
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Tested-and-Reviewed-by: Don Zickus <[email protected]>
Signed-off-by: Stephane Eranian <[email protected]>
Signed-off-by: Peter Zijlstra <[email protected]>
Link: http://lkml.kernel.org/r/20140515155644.GA3884@quad
Signed-off-by: Thomas Gleixner <[email protected]>
Diffstat (limited to 'kernel/workqueue.c')
0 files changed, 0 insertions, 0 deletions