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| author | Mohammad Athari Bin Ismail <mohammad.athari.ismail@intel.com> | 2022-01-15 17:25:15 +0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-01-15 22:38:27 +0000 |
| commit | 020a45aff1190c32b1087cd75b57fbf6bff46ea6 (patch) | |
| tree | aa52ad15a1af61478cced160997419ae593c284f /kernel/module_signature.c | |
| parent | 9a9acdccdfa430457986db608ee4ae4840107057 (diff) | |
net: phy: marvell: add Marvell specific PHY loopback
Existing genphy_loopback() is not applicable for Marvell PHY. Besides
configuring bit-6 and bit-13 in Page 0 Register 0 (Copper Control
Register), it is also required to configure same bits in Page 2
Register 21 (MAC Specific Control Register 2) according to speed of
the loopback is operating.
Tested working on Marvell88E1510 PHY for all speeds (1000/100/10Mbps).
FIXME: Based on trial and error test, it seem 1G need to have delay between
soft reset and loopback enablement.
Fixes: 014068dcb5b1 ("net: phy: genphy_loopback: add link speed configuration")
Cc: <stable@vger.kernel.org> # 5.15.x
Signed-off-by: Mohammad Athari Bin Ismail <mohammad.athari.ismail@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'kernel/module_signature.c')
0 files changed, 0 insertions, 0 deletions