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| author | Jonathan Neuschäfer <[email protected]> | 2019-03-26 19:22:58 +0100 |
|---|---|---|
| committer | Shawn Guo <[email protected]> | 2019-04-03 16:10:06 +0700 |
| commit | 1e06250983b132fe5d93e812e2ede05eb234e5a8 (patch) | |
| tree | 1d4b2da11ddab0b2ffc7834c713b47f175e876bd /kernel/bpf/arraymap.c | |
| parent | 639eb92531166a17bdb459437fbadf97459c5370 (diff) | |
clk: imx5: Fix i.MX50 ESDHC clock registers
The MUX bits for esdhc_{a,c,d}_sel are shifted by one bit within CSCMR1,
because esdhc_b_sel (ESDHC3_CLK_SEL in the Reference Manual) is extended
by one bit.
Signed-off-by: Jonathan Neuschäfer <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Diffstat (limited to 'kernel/bpf/arraymap.c')
0 files changed, 0 insertions, 0 deletions