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| author | Zhang Rui <rui.zhang@intel.com> | 2022-09-20 20:58:48 +0800 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2022-09-21 20:33:49 +0200 |
| commit | 65c0c2367e9e695b13d0d39307ebc8818bcdbd8d (patch) | |
| tree | 042342cc3dc88cb62ccea718e4cf0ed22b6817c2 /include/vdso/datapage.h | |
| parent | 06f7c08751939f33d79712590c2b21d02aba61b6 (diff) | |
intel_idle: Add AlderLake-N support
Similar to the other other AlderLake platforms, the C1 and C1E states on
ADL-N are mutually exclusive. Only one of them can be enabled at a time.
C1E is preferred on ADL-N for better energy efficiency.
C6S is also supported on this platform. Its latency is far bigger than
C6, but really close to C8 (PC8), thus it is not exposed as a separate
state.
Suggested-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Suggested-by: Vinay Kumar <vinay.kumar@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
[ rjw: Changelog edits ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'include/vdso/datapage.h')
0 files changed, 0 insertions, 0 deletions