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authorDavid S. Miller <[email protected]>2023-10-15 16:08:25 +0100
committerDavid S. Miller <[email protected]>2023-10-15 16:08:25 +0100
commit99620ea03327c5e73407f48a6994578f71951a87 (patch)
tree5de9a4d43ef857b34283feb278584233a03a66b4 /include/uapi/linux
parentcc30c6346b9e790676aacdfbb792aa16486f6396 (diff)
parent20f6677234d8105e55beca355135e94bb10fbf74 (diff)
Merge branch 'dpll-phase-offset-phase-adjust'
Arkadiusz Kubalewski says: ==================== dpll: add phase-offset and phase-adjust Improve monitoring and control over dpll devices. Allow user to receive measurement of phase difference between signals on pin and dpll (phase-offset). Allow user to receive and control adjustable value of pin's signal phase (phase-adjust). v4->v5: - rebase series on top of net-next/main, fix conflict - remove redundant attribute type definition in subset definition v3->v4: - do not increase do version of uAPI header as it is not needed (v3 did not have this change) - fix spelling around commit messages, argument descriptions and docs - add missing extack errors on failure set callbacks for pin phase adjust and frequency - remove ice check if value is already set, now redundant as checked in the dpll subsystem v2->v3: - do not increase do version of uAPI header as it is not needed v1->v2: - improve handling for error case of requesting the phase adjust set - align handling for error case of frequency set request with the approach introduced for phase adjust ==================== Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'include/uapi/linux')
-rw-r--r--include/uapi/linux/dpll.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
index 20ef0718f8dc..715a491d2727 100644
--- a/include/uapi/linux/dpll.h
+++ b/include/uapi/linux/dpll.h
@@ -138,6 +138,8 @@ enum dpll_pin_capabilities {
DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,
};
+#define DPLL_PHASE_OFFSET_DIVIDER 1000
+
enum dpll_a {
DPLL_A_ID = 1,
DPLL_A_MODULE_NAME,
@@ -173,6 +175,10 @@ enum dpll_a_pin {
DPLL_A_PIN_CAPABILITIES,
DPLL_A_PIN_PARENT_DEVICE,
DPLL_A_PIN_PARENT_PIN,
+ DPLL_A_PIN_PHASE_ADJUST_MIN,
+ DPLL_A_PIN_PHASE_ADJUST_MAX,
+ DPLL_A_PIN_PHASE_ADJUST,
+ DPLL_A_PIN_PHASE_OFFSET,
__DPLL_A_PIN_MAX,
DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)