diff options
| author | Mark Brown <broonie@kernel.org> | 2016-09-29 12:43:59 -0700 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-09-29 12:43:59 -0700 |
| commit | 4a2447b483e17c580ed1d7c9cde3267d9c3a380f (patch) | |
| tree | d4845df7d877abe55229b97f16359509c1eea140 /include/sound | |
| parent | 00f12dbd3c33bb46b2d5e122406410b325b2c77d (diff) | |
| parent | 0730bd2e2ade00d88647b13a0c17cde254ddf56e (diff) | |
Merge remote-tracking branch 'asoc/topic/intel' into asoc-next
Diffstat (limited to 'include/sound')
| -rw-r--r-- | include/sound/hda_register.h | 36 | ||||
| -rw-r--r-- | include/sound/hdaudio.h | 13 | ||||
| -rw-r--r-- | include/sound/hdaudio_ext.h | 12 |
3 files changed, 49 insertions, 12 deletions
diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h index ff1aecf325e8..0013063db7f2 100644 --- a/include/sound/hda_register.h +++ b/include/sound/hda_register.h @@ -89,6 +89,19 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_REG_SD_BDLPL 0x18 #define AZX_REG_SD_BDLPU 0x1c +/* GTS registers */ +#define AZX_REG_LLCH 0x14 + +#define AZX_REG_GTS_BASE 0x520 + +#define AZX_REG_GTSCC (AZX_REG_GTS_BASE + 0x00) +#define AZX_REG_WALFCC (AZX_REG_GTS_BASE + 0x04) +#define AZX_REG_TSCCL (AZX_REG_GTS_BASE + 0x08) +#define AZX_REG_TSCCU (AZX_REG_GTS_BASE + 0x0C) +#define AZX_REG_LLPFOC (AZX_REG_GTS_BASE + 0x14) +#define AZX_REG_LLPCL (AZX_REG_GTS_BASE + 0x18) +#define AZX_REG_LLPCU (AZX_REG_GTS_BASE + 0x1C) + /* Haswell/Broadwell display HD-A controller Extended Mode registers */ #define AZX_REG_HSW_EM4 0x100c #define AZX_REG_HSW_EM5 0x1010 @@ -242,6 +255,29 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; /* Interval used to calculate the iterating register offset */ #define AZX_DRSM_INTERVAL 0x08 +/* Global time synchronization registers */ +#define GTSCC_TSCCD_MASK 0x80000000 +#define GTSCC_TSCCD_SHIFT BIT(31) +#define GTSCC_TSCCI_MASK 0x20 +#define GTSCC_CDMAS_DMA_DIR_SHIFT 4 + +#define WALFCC_CIF_MASK 0x1FF +#define WALFCC_FN_SHIFT 9 +#define HDA_CLK_CYCLES_PER_FRAME 512 + +/* + * An error occurs near frame "rollover". The clocks in frame value indicates + * whether this error may have occurred. Here we use the value of 10. Please + * see the errata for the right number [<10] + */ +#define HDA_MAX_CYCLE_VALUE 499 +#define HDA_MAX_CYCLE_OFFSET 10 +#define HDA_MAX_CYCLE_READ_RETRY 10 + +#define TSCCU_CCU_SHIFT 32 +#define LLPC_CCU_SHIFT 32 + + /* * helpers to read the stream position */ diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h index 93e63c56f48f..56004ec8d441 100644 --- a/include/sound/hdaudio.h +++ b/include/sound/hdaudio.h @@ -245,6 +245,12 @@ struct hdac_rb { /* * HD-audio bus base driver + * + * @ppcap: pp capabilities pointer + * @spbcap: SPIB capabilities pointer + * @mlcap: MultiLink capabilities pointer + * @gtscap: gts capabilities pointer + * @drsmcap: dma resume capabilities pointer */ struct hdac_bus { struct device *dev; @@ -256,6 +262,12 @@ struct hdac_bus { void __iomem *remap_addr; int irq; + void __iomem *ppcap; + void __iomem *spbcap; + void __iomem *mlcap; + void __iomem *gtscap; + void __iomem *drsmcap; + /* codec linked list */ struct list_head codec_list; unsigned int num_codecs; @@ -335,6 +347,7 @@ static inline void snd_hdac_codec_link_down(struct hdac_device *codec) int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val); int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, unsigned int *res); +int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus); int snd_hdac_link_power(struct hdac_device *codec, bool enable); bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset); diff --git a/include/sound/hdaudio_ext.h b/include/sound/hdaudio_ext.h index b9593b201599..8660a7f10851 100644 --- a/include/sound/hdaudio_ext.h +++ b/include/sound/hdaudio_ext.h @@ -8,11 +8,6 @@ * * @bus: hdac bus * @num_streams: streams supported - * @ppcap: pp capabilities pointer - * @spbcap: SPIB capabilities pointer - * @mlcap: MultiLink capabilities pointer - * @gtscap: gts capabilities pointer - * @drsmcap: dma resume capabilities pointer * @hlink_list: link list of HDA links * @lock: lock for link mgmt * @cmd_dma_state: state of cmd DMAs: CORB and RIRB @@ -22,12 +17,6 @@ struct hdac_ext_bus { int num_streams; int idx; - void __iomem *ppcap; - void __iomem *spbcap; - void __iomem *mlcap; - void __iomem *gtscap; - void __iomem *drsmcap; - struct list_head hlink_list; struct mutex lock; @@ -54,7 +43,6 @@ void snd_hdac_ext_bus_device_remove(struct hdac_ext_bus *ebus); #define HDA_CODEC_EXT_ENTRY(_vid, _revid, _name, _drv_data) \ HDA_CODEC_REV_EXT_ENTRY(_vid, _revid, _name, _drv_data) -int snd_hdac_ext_bus_parse_capabilities(struct hdac_ext_bus *sbus); void snd_hdac_ext_bus_ppcap_enable(struct hdac_ext_bus *chip, bool enable); void snd_hdac_ext_bus_ppcap_int_enable(struct hdac_ext_bus *chip, bool enable); |