Merge tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next

Pull Allwinner clock patches from Maxime Ripard:

Some new clock units are supported, for the display clocks unsed in the
newer SoCs, and the A83T PRCM.

There is also a bunch of minor fixes for clocks that are not used by
anyone, and reworks needed by drivers that will land in 4.13.

* tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits)
  clk: sunxi-ng: Move all clock types to a library
  clk: sunxi-ng: a83t: Add support for A83T's PRCM
  dt-bindings: clock: sunxi-ccu: Add compatible string for A83T PRCM
  clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83t
  clk: sunxi-ng: a83t: Fix audio PLL divider offset
  clk: sunxi-ng: a83t: Fix PLL lock status register offset
  clk: sunxi-ng: Add driver for A83T CCU
  clk: sunxi-ng: Support multiple variable pre-dividers
  dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
  clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR()
  clk: sunxi-ng: sun5i: Export video PLLs
  clk: sunxi-ng: mux: Re-adjust parent rate
  clk: sunxi-ng: mux: Change pre-divider application function prototype
  clk: sunxi-ng: mux: split out the pre-divider computation code
  clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT
  clk: sunxi-ng: div: Switch to divider_round_rate
  clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate
  clk: divider: Make divider_round_rate take the parent clock
  clk: sunxi-ng: explicitly include linux/spinlock.h
  clk: sunxi-ng: add support for DE2 CCU
  ...

1 files changed, 13 insertions, 3 deletions

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index a428aec36ace..c59c62571e4f 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -412,9 +412,10 @@ extern const struct clk_ops clk_divider_ro_ops;
 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
 		unsigned int val, const struct clk_div_table *table,
 		unsigned long flags);
-long divider_round_rate(struct clk_hw *hw, unsigned long rate,
-		unsigned long *prate, const struct clk_div_table *table,
-		u8 width, unsigned long flags);
+long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
+			       unsigned long rate, unsigned long *prate,
+			       const struct clk_div_table *table,
+			       u8 width, unsigned long flags);
 int divider_get_val(unsigned long rate, unsigned long parent_rate,
 		const struct clk_div_table *table, u8 width,
 		unsigned long flags);
@@ -757,6 +758,15 @@ static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
 	dst->core = src->core;
 }
 
+static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
+				      unsigned long *prate,
+				      const struct clk_div_table *table,
+				      u8 width, unsigned long flags)
+{
+	return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
+					 rate, prate, table, width, flags);
+}
+
 /*
  * FIXME clock api without lock protection
  */