diff options
| author | Sergej Sawazki <[email protected]> | 2017-09-16 13:44:41 +0200 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2017-12-21 18:09:18 -0800 |
| commit | 51279ef9f64cf7eb8b3f891a2b60fa1aa4938afc (patch) | |
| tree | 8406d6a2eb541671c99e636161023430a01054df /include/linux/platform_data | |
| parent | 758231d5a80a784d60ce7c96b27f8771ca4c682b (diff) | |
clk: si5351: Add DT property to enable PLL reset
Add optional output clock DT property to enable PLL reset when a clock
output is enabled.
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Rabeeh Khoury <[email protected]>
Cc: Russell King <[email protected]>
Signed-off-by: Sergej Sawazki <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'include/linux/platform_data')
| -rw-r--r-- | include/linux/platform_data/si5351.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h index 818c5c6e203f..c71a2dd66143 100644 --- a/include/linux/platform_data/si5351.h +++ b/include/linux/platform_data/si5351.h @@ -86,6 +86,7 @@ enum si5351_disable_state { * @multisynth_src: multisynth source clock * @clkout_src: clkout source clock * @pll_master: if true, clkout can also change pll rate + * @pll_reset: if true, clkout can reset its pll * @drive: output drive strength * @rate: initial clkout rate, or default if 0 */ @@ -95,6 +96,7 @@ struct si5351_clkout_config { enum si5351_drive_strength drive; enum si5351_disable_state disable_state; bool pll_master; + bool pll_reset; unsigned long rate; }; |