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| author | David S. Miller <[email protected]> | 2017-12-13 11:22:54 -0500 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2017-12-13 11:22:54 -0500 |
| commit | f93ea3bf151daea735a3dd6bb8c3d386ee2ebac3 (patch) | |
| tree | 251b3f0f1e9d6b490d0d3bac90e94dc78f645a0e /include/linux/phy.h | |
| parent | 9cca5d2f1be941c2fbe0ac192a139fe1b93d2c3c (diff) | |
| parent | 1b0a83ac04e383e3bed21332962b90710fcf2828 (diff) | |
Merge branch 'fec-fix-refclk-enable-for-SMSC-LAN8710-20'
Richard Leitner says:
====================
net: fec: fix refclk enable for SMSC LAN8710/20
This patch series fixes the use of the SMSC LAN8710/20 with a Freescale ETH
when the refclk is generated by the FSL.
This patchset depends on the "phylib: Add device reset GPIO support" patch
submitted by Geert Uytterhoeven/Sergei Shtylyov, which was merged to
net-next as commit bafbdd527d56 ("phylib: Add device reset GPIO support").
Changes v5:
- fix reset delay calculation (max_t instead of min_t)
Changes v4:
- simplify dts parsing
- simplify reset delay evaluation and execution
- fec: ensure to only reset once during fec_enet_open()
- remove dependency notes from commit message
- add reviews and acks
Changes v3:
- use phylib to hard-reset the PHY
- implement reset delays in phylib
- add new phylib API & flag (PHY_RST_AFTER_CLK_EN) to determine if
a PHY is affected
Changes v2:
- simplify and fix fec_reset_phy function to support multiple calls
- include: linux: phy: harmonize phy_id{,_mask} type
- reset the phy instead of not turning the clock on and off
(which would have caused a power consumption regression)
====================
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'include/linux/phy.h')
| -rw-r--r-- | include/linux/phy.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/phy.h b/include/linux/phy.h index d3037e2ffbc4..c4b4715caa21 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -59,6 +59,7 @@ #define PHY_HAS_INTERRUPT 0x00000001 #define PHY_IS_INTERNAL 0x00000002 +#define PHY_RST_AFTER_CLK_EN 0x00000004 #define MDIO_DEVICE_IS_PHY 0x80000000 /* Interface Mode definitions */ @@ -853,6 +854,7 @@ int phy_aneg_done(struct phy_device *phydev); int phy_stop_interrupts(struct phy_device *phydev); int phy_restart_aneg(struct phy_device *phydev); +int phy_reset_after_clk_enable(struct phy_device *phydev); static inline void phy_device_reset(struct phy_device *phydev, int value) { |