diff options
| author | Todd Fujinaka <[email protected]> | 2014-07-10 01:47:15 -0700 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2014-07-10 01:48:28 -0700 |
| commit | 948264879b6894dc389a44b99fae4f0b72932619 (patch) | |
| tree | bcec9d0dd4a6ddca75038cbc44227fb25e05099e /include/linux/fpga/fpga-mgr.h | |
| parent | b4df480f68ae03b5dd4ab0db56536fbcec741705 (diff) | |
igb: Workaround for i210 Errata 25: Slow System Clock
On some devices, the internal PLL circuit occasionally provides the
wrong clock frequency after power up. The probability of failure is less
than one failure per 1000 power cycles. When the failure occurs, the
internal clock frequency is around 1/20 of the correct frequency.
Cc: stable <[email protected]>
Signed-off-by: Todd Fujinaka <[email protected]>
Tested-by: Aaron Brown <[email protected]>
Signed-off-by: Jeff Kirsher <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'include/linux/fpga/fpga-mgr.h')
0 files changed, 0 insertions, 0 deletions