diff options
| author | Dragos Bogdan <[email protected]> | 2020-04-29 10:21:29 +0300 |
|---|---|---|
| committer | Jonathan Cameron <[email protected]> | 2020-05-03 12:35:03 +0100 |
| commit | 5e4f99a6b788047b0b8a7496c2e0c8f372f6edf2 (patch) | |
| tree | 1920a89718d5fdb07ced83a470358dcb65edf6cb /include/linux/fpga/fpga-mgr.h | |
| parent | aad4742fbf0a560c25827adb58695a4497ffc204 (diff) | |
staging: iio: ad2s1210: Fix SPI reading
If the serial interface is used, the 8-bit address should be latched using
the rising edge of the WR/FSYNC signal.
This basically means that a CS change is required between the first byte
sent, and the second one.
This change splits the single-transfer transfer of 2 bytes into 2 transfers
with a single byte, and CS change in-between.
Note fixes tag is not accurate, but reflects a point beyond which there
are too many refactors to make backporting straight forward.
Fixes: b19e9ad5e2cb ("staging:iio:resolver:ad2s1210 general driver cleanup.")
Signed-off-by: Dragos Bogdan <[email protected]>
Signed-off-by: Alexandru Ardelean <[email protected]>
Cc: <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Diffstat (limited to 'include/linux/fpga/fpga-mgr.h')
0 files changed, 0 insertions, 0 deletions