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authorJoseph Lo <[email protected]>2013-01-15 22:10:38 +0000
committerStephen Warren <[email protected]>2013-01-28 11:20:38 -0700
commit5c1350bdfcebf47b3b6f83d62e5860259858a54a (patch)
treea44b2ec6cf784e7979a0be813205a1e43d6ec749 /include/linux/fpga/fpga-mgr.h
parentd4b92fb2535a5b35cab9713d6793f1674cc45ba7 (diff)
ARM: tegra20: cpuidle: add powered-down state for secondary CPU
The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <[email protected]> Gary King <[email protected]> Signed-off-by: Joseph Lo <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
Diffstat (limited to 'include/linux/fpga/fpga-mgr.h')
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