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author | Yan Markman <[email protected]> | 2016-10-16 00:22:32 +0300 |
---|---|---|
committer | Gregory CLEMENT <[email protected]> | 2017-10-26 17:41:26 +0200 |
commit | cda80a82ac3e89309706c027ada6ab232be1d640 (patch) | |
tree | 15f22dc1162f04a8a6d48360d7b70d3755639e4a /include/linux/fpga/fpga-bridge.h | |
parent | 2bbbd96357ce76cc45ec722c00f654aa7b189112 (diff) |
ARM: dts: mvebu: pl310-cache disable double-linefill
Under heavy system stress mvebu SoC using Cortex A9 sporadically
encountered instability issues.
The "double linefill" feature of L2 cache was identified as causing
dependency between read and write which lead to the deadlock.
Especially, it was the cause of deadlock seen under heavy PCIe traffic,
as this dependency violates PCIE overtaking rule.
Fixes: c8f5a878e554 ("ARM: mvebu: use DT properties to fine-tune the L2 configuration")
Cc: [email protected]
Signed-off-by: Yan Markman <[email protected]>
Signed-off-by: Igal Liberman <[email protected]>
Signed-off-by: Nadav Haklai <[email protected]>
[[email protected]: reformulate commit log, add Armada
375 and add Fixes tag]
Signed-off-by: Gregory CLEMENT <[email protected]>
Diffstat (limited to 'include/linux/fpga/fpga-bridge.h')
0 files changed, 0 insertions, 0 deletions