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authorBogdan Purcareata <[email protected]>2017-10-29 08:20:42 +0000
committerGreg Kroah-Hartman <[email protected]>2017-11-03 16:19:27 +0100
commit8a4fd8778b929ac9459ad740f5e9812b2aa87bca (patch)
treef14593151626a3f7c03982139933f2b813522332 /include/linux/fpga/fpga-bridge.h
parent3c2192863f2dfc64384a6c201dcf96a887367b30 (diff)
staging: fsl-dpaa2/eth: Change RX buffer alignment
The WRIOP hardware block v1.0.0 (found on LS2080A board) requires data in RX buffers to be aligned to 256B, but newer revisions (e.g. on LS2088A, LS1088A) only require 64B alignment. Check WRIOP version and decide at runtime which alignment requirement to configure for ingress buffers. Signed-off-by: Bogdan Purcareata <[email protected]> Signed-off-by: Ioana Radulescu <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'include/linux/fpga/fpga-bridge.h')
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