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authorCyrille Pitchen <[email protected]>2020-04-03 06:12:26 +0000
committerAlexandre Belloni <[email protected]>2020-04-13 13:00:09 +0200
commit51cca920ce84356d53068ac83a53ba8c45879a0e (patch)
tree6f00d5a2e2376d1c6fd15657e56267187497fd8f /include/linux/fpga/fpga-bridge.h
parent0fd3a8f58f78b498784b72c1971c225c4e69ddac (diff)
ARM: dts: at91: sama5d2_xplained: Add QSPI0 + SPI NOR memory nodes
This patch enables the QSPI0 controller, configures its pin muxing and declares a jedec,spi-nor memory. sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash memory which advertises a maximum frequency of 80MHz for Quad IO Fast Read. Set the spi-max-frequency to 80MHz knowing that actually the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz. Signed-off-by: Cyrille Pitchen <[email protected]> Tested-by: Tudor Ambarus <[email protected]> Signed-off-by: Tudor Ambarus <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alexandre Belloni <[email protected]>
Diffstat (limited to 'include/linux/fpga/fpga-bridge.h')
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