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authorLin Ming <[email protected]>2010-03-18 18:33:12 +0800
committerIngo Molnar <[email protected]>2010-03-18 17:04:02 +0100
commitcb7d6b5053e86598735d9af19930f5929f007b7f (patch)
treeb707d913470443c05bd637d4b7fbab3926e0ba1c /include/linux/debugobjects.h
parentf34edbc1cdb0f8f83d94e1d668dd6e41abf0defb (diff)
perf, x86: Add cache events for the Pentium-4 PMU
Move the HT bit setting code from p4_pmu_event_map to p4_hw_config. So the cache events can get HT bit set correctly. Tested on my P4 desktop, below 6 cache events work: L1-dcache-load-misses LLC-load-misses dTLB-load-misses dTLB-store-misses iTLB-loads iTLB-load-misses Signed-off-by: Lin Ming <[email protected]> Reviewed-by: Cyrill Gorcunov <[email protected]> Cc: Peter Zijlstra <[email protected]> LKML-Reference: <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
Diffstat (limited to 'include/linux/debugobjects.h')
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