diff options
| author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2017-06-20 17:24:23 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:08:10 -0400 |
| commit | cb26f8925c50aa244ac34a72ac232e4c7dbd6f98 (patch) | |
| tree | 105e6db4662b1bd3020ff2aef955fb022cc463cc /drivers | |
| parent | 92af86fa7cba07aeec2f5f455b5ad981aff6013d (diff) | |
drm/amd/display: use different sr latencies for dpm0 dcn bw calc
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 0aa6662650cc..9cb08365e2b6 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -906,6 +906,16 @@ bool dcn_validate_bandwidth( scaler_settings_calculation(v); mode_support_and_system_configuration(v); + if (v->voltage_level == 0) { + struct core_dc *dc_core = DC_TO_CORE(&dc->public); + + v->sr_enter_plus_exit_time = 9.466f; + v->sr_exit_time = 7.849f; + dc_core->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; + dc_core->dml.soc.sr_exit_time_us = v->sr_exit_time; + mode_support_and_system_configuration(v); + } + if (v->voltage_level != 5) { float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second; if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65) @@ -1013,6 +1023,14 @@ bool dcn_validate_bandwidth( &dc->dml, context, pool); } + if (v->voltage_level == 0) { + struct core_dc *dc_core = DC_TO_CORE(&dc->public); + + dc_core->dml.soc.sr_enter_plus_exit_time_us = + dc_core->dcn_soc.sr_enter_plus_exit_time; + dc_core->dml.soc.sr_exit_time_us = dc_core->dcn_soc.sr_exit_time; + } + kernel_fpu_end(); return v->voltage_level != 5; } |