diff options
| author | Maxime Ripard <maxime@cerno.tech> | 2022-09-14 12:22:18 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2022-09-14 12:22:18 +0100 |
| commit | a108772d03d8bdb43258218b00bfe43bbe1e8800 (patch) | |
| tree | 11b1f413ab384f2b5de0773f01b6886e2c601f8b /drivers/usb/dwc3/core.h | |
| parent | 75cebd664d57a78af3e46c14bd2659df0a08847b (diff) | |
| parent | 213cb76ddc8b875e772f9f4d173feefa122716af (diff) | |
Merge drm/drm-next into drm-misc-next
We need 6.0-rc1 to merge the backlight rework PR.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to 'drivers/usb/dwc3/core.h')
| -rw-r--r-- | drivers/usb/dwc3/core.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 81c486b3941c..4fe4287dc934 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -231,6 +231,7 @@ /* Global Configuration Register */ #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) +#define DWC3_GCTL_PWRDNSCALE_MASK GENMASK(31, 19) #define DWC3_GCTL_U2RSTECN BIT(16) #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) #define DWC3_GCTL_CLK_BUS (0) @@ -1086,6 +1087,8 @@ struct dwc3_scratchpad_array { * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled. * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled. * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3 + * @async_callbacks: if set, indicate that async callbacks will be used. + * * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists * in GUSB2PHYCFG, specify that USB2 PHY doesn't * provide a free-running PHY clock. |