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authorMatthias Schiffer <[email protected]>2020-09-02 15:30:43 +0200
committerMark Brown <[email protected]>2020-09-17 17:40:08 +0100
commitdf44bc16e616809172cda90fd816596ded4ea219 (patch)
treeb65919b444737bd3f083dbbaa94d7a322cc3e073 /drivers/usb/cdns3/cdns3-ti.c
parent251e5c8694db01cd10828e39c07f90d958d7b303 (diff)
ASoC: codec: tlv320aic32x4: do software reset before clock registration
To avoid the actual PLL settings to differ from the state expected by the clock driver, the codec should only be fully reset before the clocks are registered. But we also need to ensure that the software reset happens at all before clock registration, as not all boards have a reset GPIO. Move the software reset from aic32x4_component_probe() to aic32x4_probe() and reorder the reset and registration sequence: 1. Reset via GPIO (if available) 2. Reset via software 3. Register component 4. Register clocks Note that aic32x4_component_probe() is only called after aic32x4_probe() has finished, so the reset in aic32x4_component_probe() was happening too late. Signed-off-by: Matthias Schiffer <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'drivers/usb/cdns3/cdns3-ti.c')
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