drm/amdgpu: normalize registers as local xcc to read/write in gfx_v9_4_3

[WHY]
sriov has the higher bit violation when flushing tlb

[HOW]
normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit violation
RLCG will mask xcd out and always assume it's accessing its own xcd

v2
add check in wait mem that only do the normalization on regspace

Signed-off-by: Jane Jian <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Acked-by: Christian König <[email protected]>
Acked-by: Yiqing Yao <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

0 files changed, 0 insertions, 0 deletions