diff options
| author | Biju Das <[email protected]> | 2021-11-12 08:10:00 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2021-11-19 11:34:56 +0100 |
| commit | 86e122c0754951094a3857870ad9f4022e056f6b (patch) | |
| tree | 2c36188978419b83b784cce13725e3c23f21093b /drivers/usb/cdns3/cdns3-debug.h | |
| parent | e5f7e81ee430acb6d1fa9a6323fe645bd52e0b9c (diff) | |
clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
Core clock "I" is sourced from CPG_PL1_DDIV which controls CPU
frequency. Define CPG_PL1_DDIV, so that we can register it as a
clock divider in later patch.
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'drivers/usb/cdns3/cdns3-debug.h')
0 files changed, 0 insertions, 0 deletions