diff options
| author | Mark Brown <broonie@kernel.org> | 2019-07-24 17:00:06 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-07-24 17:00:06 +0100 |
| commit | 27988c96687667e74df1a9a3b8662519bc1c29c9 (patch) | |
| tree | 0aa67d365e8d544bf48a4de9ae94d7f8536de073 /drivers/spi/spi-stm32-qspi.c | |
| parent | 8f46e22b5ac692b48d04bb722547ca17b66dda02 (diff) | |
| parent | 5f9e832c137075045d15cd6899ab0505cfb2ca4b (diff) | |
Merge tag 'v5.3-rc1' into regulator-5.3
Linus 5.3-rc1
Diffstat (limited to 'drivers/spi/spi-stm32-qspi.c')
| -rw-r--r-- | drivers/spi/spi-stm32-qspi.c | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c index 42f8e3c6aa1f..655e4afbfb2a 100644 --- a/drivers/spi/spi-stm32-qspi.c +++ b/drivers/spi/spi-stm32-qspi.c @@ -29,7 +29,7 @@ #define CR_SSHIFT BIT(4) #define CR_DFM BIT(6) #define CR_FSEL BIT(7) -#define CR_FTHRES_MASK GENMASK(12, 8) +#define CR_FTHRES_SHIFT 8 #define CR_TEIE BIT(16) #define CR_TCIE BIT(17) #define CR_FTIE BIT(18) @@ -245,12 +245,8 @@ static int stm32_qspi_tx_dma(struct stm32_qspi *qspi, writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR); t_out = sgt.nents * STM32_COMP_TIMEOUT_MS; - if (!wait_for_completion_interruptible_timeout(&qspi->dma_completion, - msecs_to_jiffies(t_out))) - err = -ETIMEDOUT; - - if (dma_async_is_tx_complete(dma_ch, cookie, - NULL, NULL) != DMA_COMPLETE) + if (!wait_for_completion_timeout(&qspi->dma_completion, + msecs_to_jiffies(t_out))) err = -ETIMEDOUT; if (err) @@ -304,7 +300,7 @@ static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi, cr = readl_relaxed(qspi->io_base + QSPI_CR); writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR); - if (!wait_for_completion_interruptible_timeout(&qspi->data_completion, + if (!wait_for_completion_timeout(&qspi->data_completion, msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) { err = -ETIMEDOUT; } else { @@ -463,7 +459,7 @@ static int stm32_qspi_setup(struct spi_device *spi) flash->presc = presc; mutex_lock(&qspi->lock); - qspi->cr_reg = FIELD_PREP(CR_FTHRES_MASK, 3) | CR_SSHIFT | CR_EN; + qspi->cr_reg = 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN; writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR); /* set dcr fsize to max address */ |