diff options
| author | Yang Yingliang <yangyingliang@huawei.com> | 2022-10-18 10:31:47 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2022-11-09 22:01:31 +0000 |
| commit | 73e770f085023da327dc9ffeb6cd96b0bb22d97e (patch) | |
| tree | cd2bec565e969d8ff3a3cd87454c7cf77c4b8de4 /drivers/soc | |
| parent | 9abf2313adc1ca1b6180c508c25f22f9395cc780 (diff) | |
soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()
Add missing iounmap() before return error from sifive_ccache_init().
Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'drivers/soc')
| -rw-r--r-- | drivers/soc/sifive/sifive_ccache.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 1c171150e878..25019c16d8ae 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -222,13 +222,16 @@ static int __init sifive_ccache_init(void) if (!ccache_base) return -ENOMEM; - if (of_property_read_u32(np, "cache-level", &level)) - return -ENOENT; + if (of_property_read_u32(np, "cache-level", &level)) { + rc = -ENOENT; + goto err_unmap; + } intr_num = of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { pr_err("No interrupts property\n"); - return -ENODEV; + rc = -ENODEV; + goto err_unmap; } for (i = 0; i < intr_num; i++) { @@ -237,7 +240,7 @@ static int __init sifive_ccache_init(void) NULL); if (rc) { pr_err("Could not request IRQ %d\n", g_irq[i]); - return rc; + goto err_unmap; } } @@ -250,6 +253,10 @@ static int __init sifive_ccache_init(void) setup_sifive_debug(); #endif return 0; + +err_unmap: + iounmap(ccache_base); + return rc; } device_initcall(sifive_ccache_init); |