dmaengine: ste_dma40: don't allow high priority dest event lines

Hardware bug: when a logical channel is triggerred by a high priority
destination event line, an extra packet transaction is generated in case
of important data write response latency on previous logical channel A
and if the source transfer of current logical channel B is already
completed and if no other channel with a higher priority than B is
waiting for execution.

Software workaround: do not set the high priority level for the
destination event lines that trigger logical channels.

Signed-off-by: Rabin Vincent <[email protected]>
Reviewed-by: Shreshtha Kumar Sahu <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Acked-by: Vinod Koul <[email protected]>
Signed-off-by: Fabio Baltieri <[email protected]>

0 files changed, 0 insertions, 0 deletions