omap3/4: uart: fix full-fifo write abort

This patch is addition to the already merged commit on non-empty
uart fifo read abort. "ce13d4716a276f4331d78ba28a5093a63822ab95"

OMAP3630 and OMAP4430 UART IP blocks have a restriction on TX FIFO
too. If you try to write to the tx fifo when it is full, the system aborts.

More details on this thread are here:
http://www.mail-archive.com/[email protected]/msg19447.html

This can be easily reproducible by not suppressing interconnect errors or
long duration testing where continuous prints over console from multiple
threads. This patch is addressing the issue by ensuring that write is
not issued while fifo is full. A timeout is added to avoid any hang
on fifo-full for 10 mS which is unlikely case.

Patch is validated on OMAP3630 and OMAP4 SDP.

V2 version removed the additional 1 uS on every TX as per
Tony's suggestion

Signed-off-by: Woodruff Richard <[email protected]>
Signed-off-by: Santosh Shilimkar <[email protected]>
CC: Ghorai Sukumar <[email protected]>
Reviewed-by: Paul Walmsley <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>

0 files changed, 0 insertions, 0 deletions