drm/i915: provide interface for audio driver to query cdclk

For Haswell and Broadwell, if the display power well has been disabled,
the display audio controller divider values EM4 M VALUE and EM5 N VALUE
will have been lost. The CDCLK frequency is required for reprogramming them
to generate 24MHz HD-A link BCLK. So provide a private interface for the
audio driver to query CDCLK.

This is a stopgap solution until a more generic interface between audio
and display drivers has been implemented.

Signed-off-by: Jani Nikula <[email protected]>
Reviewed-by: Damien Lespiau <[email protected]>
Signed-off-by: Mengdong Lin <[email protected]>
Cc: <[email protected]>
Signed-off-by: Takashi Iwai <[email protected]>

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