drm/amd/display: fix a pipe mapping error in dcn32_fpu

[why]
In dcn32 DML pipes are ordered the same as dc pipes but only for used
pipes. For example, if dc pipe 1 and 2 are used, their dml pipe indices
would be 0 and 1 respectively. However
update_pipe_slice_table_with_split_flags doesn't skip indices for free
pipes. This causes us to not reference correct dml pipe output when
building pipe topology.

[how]
Use two variables to iterate dc and dml pipes respectively and only
increment dml pipe index when current dc pipe is not free.

Cc: [email protected] # 6.1+
Reviewed-by: Chaitanya Dhere <[email protected]>
Acked-by: Hamza Mahfooz <[email protected]>
Signed-off-by: Wenjing Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

0 files changed, 0 insertions, 0 deletions