diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-07-05 12:43:12 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2022-07-07 10:36:00 +0530 |
| commit | fc270d136a157b03d6c96590242ad5401a9f1ed2 (patch) | |
| tree | 41635fb0f110e849c99eb6f132da453cd7bb76a6 /drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h | |
| parent | 25ad4a4cfeff80021f041c71b4968adf470f9ec3 (diff) | |
phy: qcom-qmp: split PCS_UFS V3 symbols to separate header
Several registers defined in the PCS V3 namespace in reality belong to
the PCS_UFS V3 register space. Move them to the separate header and
rename them to explicitly mention PCS_UFS. While we are at it, correct
one register in the msm8998_usb3_pcs_tbl table to use PCS register name.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-21-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h index 0b023df19126..ac13f2989a73 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h @@ -14,8 +14,6 @@ #define QPHY_V3_PCS_TXMGN_V3 0x018 #define QPHY_V3_PCS_TXMGN_V4 0x01c #define QPHY_V3_PCS_TXMGN_LS 0x020 -#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c -#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c @@ -53,15 +51,9 @@ #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 -#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 -#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 -#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c -#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 -#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc -#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 |