Merge branch 'pci/controller/rockchip'

- Remove writes to unused registers (Rick Wertenbroek)

- Write endpoint Device ID using correct register (Rick Wertenbroek)

- Assert PCI Configuration Enable bit after probe so endpoint responds
  instead of generating Request Retry Status messages (Rick Wertenbroek)

- Poll waiting for PHY PLLs to lock (Rick Wertenbroek)

- Update RK3399 example DT binding to be valid (Rick Wertenbroek)

- Use RK3399 PCIE_CLIENT_LEGACY_INT_CTRL to generate INTx instead of
  manually generating PCIe message (Rick Wertenbroek)

- Use multiple windows to avoid address translation conflicts (Rick
  Wertenbroek)

- Use u32 (not u16) when accessing 32-bit registers (Rick Wertenbroek)

- Hide MSI-X Capability, since RK3399 can't generate MSI-X (Rick
  Wertenbroek)

- Set endpoint controller required alignment to 256 (Damien Le Moal)

* pci/controller/rockchip:
  PCI: rockchip: Set address alignment for endpoint mode
  PCI: rockchip: Don't advertise MSI-X in PCIe capabilities
  PCI: rockchip: Use u32 variable to access 32-bit registers
  PCI: rockchip: Fix window mapping and address translation for endpoint
  PCI: rockchip: Fix legacy IRQ generation for RK3399 PCIe endpoint core
  dt-bindings: PCI: Update the RK3399 example to a valid one
  PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked
  PCI: rockchip: Assert PCI Configuration Enable bit after probe
  PCI: rockchip: Write PCI Device ID to correct register
  PCI: rockchip: Remove writes to unused registers

1 files changed, 17 insertions, 0 deletions

diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
index 990a00e08bc5..1aa84035a8bc 100644
--- a/drivers/pci/controller/pcie-rockchip.c
+++ b/drivers/pci/controller/pcie-rockchip.c
@@ -14,6 +14,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/gpio/consumer.h>
+#include <linux/iopoll.h>
 #include <linux/of_pci.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
@@ -153,6 +154,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
 }
 EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);
 
+#define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr)
+/* 100 ms max wait time for PHY PLLs to lock */
+#define RK_PHY_PLL_LOCK_TIMEOUT_US 100000
+/* Sleep should be less than 20ms */
+#define RK_PHY_PLL_LOCK_SLEEP_US 1000
+
 int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 {
 	struct device *dev = rockchip->dev;
@@ -254,6 +261,16 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 		}
 	}
 
+	err = readx_poll_timeout(rockchip_pcie_read_addr,
+				 PCIE_CLIENT_SIDE_BAND_STATUS,
+				 regs, !(regs & PCIE_CLIENT_PHY_ST),
+				 RK_PHY_PLL_LOCK_SLEEP_US,
+				 RK_PHY_PLL_LOCK_TIMEOUT_US);
+	if (err) {
+		dev_err(dev, "PHY PLLs could not lock, %d\n", err);
+		goto err_power_off_phy;
+	}
+
 	/*
 	 * Please don't reorder the deassert sequence of the following
 	 * four reset pins.