Merge branch 'pci/ctrl/tegra194'

- Fix tegra_pcie_config_ep() power management in error path (Miaoqian Lin)

- Convert DT binding to json-schema (Vidya Sagar)

- Add DT bindings and driver support for Tegra234 Root Port and Endpoint
  mode (Vidya Sagar)

- Disable MSI for Tegra234 Root Ports so they use INTx for all events (PCIe
  doesn't allow mixing INTx and MSI/MSI-X) (Vidya Sagar)

- Search for Vendor-Specific RAS-DEC capability instead of hard-coding
  offset (Vidya Sagar)

- Fix unintentional APPL_INTR_STATUS_L0 value overwrite in Root Port
  interrupt handling (Vidya Sagar)

- Clear Bandwidth Management interrupt status bit to avoid interrupt storm
  (Vidya Sagar)

- Set default Max Payload Size to 256 bytes (Vidya Sagar)

- Fix offset when clearing bit in Data Link Feature capability (Vidya
  Sagar)

- Extend Endpoint mode support to devices beyond Controller-5 (Vidya Sagar)

* pci/ctrl/tegra194:
  PCI: tegra194: Add Tegra234 PCIe support
  PCI: tegra194: Extend Endpoint mode support
  PCI: tegra194: Fix link up retry sequence
  PCI: tegra194: Clean up the exit path for Endpoint mode
  PCI: tegra194: Enable support for 256 Byte payload
  PCI: tegra194: Clear bandwidth management status
  PCI: tegra194: Fix Root Port interrupt handling
  PCI: tegra194: Find RAS DES PCIe capability offset
  Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie"
  PCI: Disable MSI for Tegra234 Root Ports
  dt-bindings: PCI: tegra234: Add schema for tegra234 Endpoint mode
  dt-bindings: PCI: tegra234: Add schema for tegra234 Root Port mode
  dt-bindings: PCI: tegra194: Convert to json-schema
  PCI: tegra194: Fix PM error handling in tegra_pcie_config_ep()

# Conflicts:
#	drivers/pci/controller/dwc/pcie-designware.h
#	drivers/pci/controller/dwc/pcie-tegra194.c

1 files changed, 32 insertions, 0 deletions

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 557e1d22dc63..09b887093a84 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -162,6 +162,38 @@
 #define PCIE_PL_CHK_REG_ERR_ADDR			0xB28
 
 /*
+ * iATU Unroll-specific register definitions
+ * From 4.80 core version the address translation will be made by unroll
+ */
+#define PCIE_ATU_UNR_REGION_CTRL1	0x00
+#define PCIE_ATU_UNR_REGION_CTRL2	0x04
+#define PCIE_ATU_UNR_LOWER_BASE		0x08
+#define PCIE_ATU_UNR_UPPER_BASE		0x0C
+#define PCIE_ATU_UNR_LOWER_LIMIT	0x10
+#define PCIE_ATU_UNR_LOWER_TARGET	0x14
+#define PCIE_ATU_UNR_UPPER_TARGET	0x18
+#define PCIE_ATU_UNR_UPPER_LIMIT	0x20
+
+/*
+ * RAS-DES register definitions
+ */
+#define PCIE_RAS_DES_EVENT_COUNTER_CONTROL	0x8
+#define EVENT_COUNTER_ALL_CLEAR		0x3
+#define EVENT_COUNTER_ENABLE_ALL	0x7
+#define EVENT_COUNTER_ENABLE_SHIFT	2
+#define EVENT_COUNTER_EVENT_SEL_MASK	GENMASK(7, 0)
+#define EVENT_COUNTER_EVENT_SEL_SHIFT	16
+#define EVENT_COUNTER_EVENT_Tx_L0S	0x2
+#define EVENT_COUNTER_EVENT_Rx_L0S	0x3
+#define EVENT_COUNTER_EVENT_L1		0x5
+#define EVENT_COUNTER_EVENT_L1_1	0x7
+#define EVENT_COUNTER_EVENT_L1_2	0x8
+#define EVENT_COUNTER_GROUP_SEL_SHIFT	24
+#define EVENT_COUNTER_GROUP_5		0x5
+
+#define PCIE_RAS_DES_EVENT_COUNTER_DATA		0xc
+
+/*
  * The default address offset between dbi_base and atu_base. Root controller
  * drivers are not required to initialize atu_base if the offset matches this
  * default; the driver core automatically derives atu_base from dbi_base using