diff options
| author | Vidya Sagar <vidyas@nvidia.com> | 2020-12-30 22:27:23 +0530 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2021-02-24 10:59:30 -0600 |
| commit | 6104033bd25ef48d2013220f66632d8b0fc8cddb (patch) | |
| tree | 4d0f038cfd953f4a44ec834b6d570d15198f40f3 /drivers/pci/controller/dwc/pcie-designware-host.c | |
| parent | 7c53f6b671f4aba70ff15e1b05148b10d58c2837 (diff) | |
PCI: dwc: Work around ECRC configuration issue
DesignWare core has a TLP digest (TD) override bit in one of the control
registers of ATU. This bit also needs to be programmed for proper ECRC
functionality. This is currently identified as an issue with DesignWare
IP version 4.90a.
[bhelgaas: fix typos/grammar errors]
Link: https://lore.kernel.org/r/20201230165723.673-1-vidyas@nvidia.com
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware-host.c')
0 files changed, 0 insertions, 0 deletions