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| author | Bjorn Helgaas <bhelgaas@google.com> | 2023-10-28 13:31:05 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2023-10-28 13:31:05 -0500 |
| commit | 5897c174028a6a05169b6ecdbcd20fe4d1a8bcda (patch) | |
| tree | 184ebbe7e6fff66e04d53bbc416ecde1f538612f /drivers/pci/controller/dwc/pcie-designware-ep.c | |
| parent | 65de3fd8f5c8a910e5bebc0607f8790158ad673a (diff) | |
| parent | 8a0395578a9bb8937d1cc88c3f2e17e437467c2d (diff) | |
Merge branch 'pci/field-get'
- Use FIELD_GET()/FIELD_PREP() when possible throughout drivers/pci/ (Ilpo
Järvinen, Bjorn Helgaas)
- Rework DPC control programming for clarity (Ilpo Järvinen)
* pci/field-get:
PCI/portdrv: Use FIELD_GET()
PCI/VC: Use FIELD_GET()
PCI/PTM: Use FIELD_GET()
PCI/PME: Use FIELD_GET()
PCI/ATS: Use FIELD_GET()
PCI/ATS: Show PASID Capability register width in bitmasks
PCI: Use FIELD_GET() in Sapphire RX 5600 XT Pulse quirk
PCI: Use FIELD_GET()
PCI/MSI: Use FIELD_GET/PREP()
PCI/DPC: Use defines with DPC reason fields
PCI/DPC: Use defined fields with DPC_CTL register
PCI/DPC: Use FIELD_GET()
PCI: hotplug: Use FIELD_GET/PREP()
PCI: dwc: Use FIELD_GET/PREP()
PCI: cadence: Use FIELD_GET()
PCI: Use FIELD_GET() to extract Link Width
PCI: mvebu: Use FIELD_PREP() with Link Width
PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields
# Conflicts:
# drivers/pci/controller/dwc/pcie-tegra194.c
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware-ep.c')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware-ep.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index d34a5e87ad18..f6207989fc6a 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -6,6 +6,7 @@ * Author: Kishon Vijay Abraham I <kishon@ti.com> */ +#include <linux/bitfield.h> #include <linux/of.h> #include <linux/platform_device.h> @@ -350,7 +351,7 @@ static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no) if (!(val & PCI_MSI_FLAGS_ENABLE)) return -EINVAL; - val = (val & PCI_MSI_FLAGS_QSIZE) >> 4; + val = FIELD_GET(PCI_MSI_FLAGS_QSIZE, val); return val; } @@ -373,7 +374,7 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no, reg = ep_func->msi_cap + func_offset + PCI_MSI_FLAGS; val = dw_pcie_readw_dbi(pci, reg); val &= ~PCI_MSI_FLAGS_QMASK; - val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK; + val |= FIELD_PREP(PCI_MSI_FLAGS_QMASK, interrupts); dw_pcie_dbi_ro_wr_en(pci); dw_pcie_writew_dbi(pci, reg, val); dw_pcie_dbi_ro_wr_dis(pci); @@ -600,7 +601,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, reg = ep_func->msix_cap + func_offset + PCI_MSIX_TABLE; tbl_offset = dw_pcie_readl_dbi(pci, reg); - bir = (tbl_offset & PCI_MSIX_TABLE_BIR); + bir = FIELD_GET(PCI_MSIX_TABLE_BIR, tbl_offset); tbl_offset &= PCI_MSIX_TABLE_OFFSET; msix_tbl = ep->epf_bar[bir]->addr + tbl_offset; |