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author | Bjorn Helgaas <bhelgaas@google.com> | 2023-06-26 12:59:59 -0500 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2023-06-26 12:59:59 -0500 |
commit | 9f5eb1bf55121a5729c7ca27b4276b51d4ae3048 (patch) | |
tree | 6923582d868b9e4a187da06661741307af0a5d87 /drivers/pci/controller/dwc/pci-imx6.c | |
parent | 9cd5f2cec7e51c7254cda228e6b9950e994be401 (diff) | |
parent | 7e6689b34a815bd379dfdbe9855d36f395ef056c (diff) |
Merge branch 'pci/controller/rockchip'
- Remove writes to unused registers (Rick Wertenbroek)
- Write endpoint Device ID using correct register (Rick Wertenbroek)
- Assert PCI Configuration Enable bit after probe so endpoint responds
instead of generating Request Retry Status messages (Rick Wertenbroek)
- Poll waiting for PHY PLLs to lock (Rick Wertenbroek)
- Update RK3399 example DT binding to be valid (Rick Wertenbroek)
- Use RK3399 PCIE_CLIENT_LEGACY_INT_CTRL to generate INTx instead of
manually generating PCIe message (Rick Wertenbroek)
- Use multiple windows to avoid address translation conflicts (Rick
Wertenbroek)
- Use u32 (not u16) when accessing 32-bit registers (Rick Wertenbroek)
- Hide MSI-X Capability, since RK3399 can't generate MSI-X (Rick
Wertenbroek)
- Set endpoint controller required alignment to 256 (Damien Le Moal)
* pci/controller/rockchip:
PCI: rockchip: Set address alignment for endpoint mode
PCI: rockchip: Don't advertise MSI-X in PCIe capabilities
PCI: rockchip: Use u32 variable to access 32-bit registers
PCI: rockchip: Fix window mapping and address translation for endpoint
PCI: rockchip: Fix legacy IRQ generation for RK3399 PCIe endpoint core
dt-bindings: PCI: Update the RK3399 example to a valid one
PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked
PCI: rockchip: Assert PCI Configuration Enable bit after probe
PCI: rockchip: Write PCI Device ID to correct register
PCI: rockchip: Remove writes to unused registers
Diffstat (limited to 'drivers/pci/controller/dwc/pci-imx6.c')
0 files changed, 0 insertions, 0 deletions