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authorHariprasad Kelam <hkelam@marvell.com>2022-09-10 13:24:14 +0530
committerDavid S. Miller <davem@davemloft.net>2022-09-17 20:13:41 +0100
commit2958d17a898416c6193431676f6130b68a2cb9fc (patch)
tree95fcf3ccdc68f94f08e18aefdd4ea4b76a271ba6 /drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h
parenta8025e7946a2b18c4ac17b36fde528d2f6262bdd (diff)
octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
Add support for ptp 1-step mode using timecounter. The seconds and nanoseconds to be updated in PTP header are calculated by adding the timecounter offset to the free running PTP clock counter time. The PF driver periodically gets the PTP clock time using AF mbox. The 1-step support uses HW feature to update correction field rather than OriginTimestamp field in PTP header. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h')
-rw-r--r--drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h
index 4bbd12ff26e6..aa205a0d158f 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h
@@ -236,8 +236,15 @@ struct nix_sqe_sg_s {
/* NIX send memory subdescriptor structure */
struct nix_sqe_mem_s {
- u64 offset : 16; /* W0 */
- u64 rsvd_51_16 : 36;
+ u64 start_offset : 8;
+ u64 rsvd_11_8 : 4;
+ u64 rsvd_12 : 1;
+ u64 udp_csum_crt : 1;
+ u64 update64 : 1;
+ u64 rsvd_15_16 : 1;
+ u64 base_ns : 32;
+ u64 step_type : 1;
+ u64 rsvd_51_49 : 3;
u64 per_lso_seg : 1;
u64 wmem : 1;
u64 dsz : 2;