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| author | Mark Bloch <mbloch@nvidia.com> | 2021-03-10 23:09:14 -0800 |
|---|---|---|
| committer | Saeed Mahameed <saeedm@nvidia.com> | 2021-03-12 13:07:46 -0800 |
| commit | c3e666f1ada9cbfbe5465f122f9a2d63ddfd25ed (patch) | |
| tree | 2b7d1bac2f8d53f2602eab1a5c0e8e8bb628394d /drivers/net/ethernet/intel/ice/ice_lib.c | |
| parent | 3a46f4fb55ffd46e475e3fc53b1252f722cf647e (diff) | |
net/mlx5: Add IFC bits needed for single FDB mode
Currently we operate in a mode where each eswitch manager has a separate
FDB. In order to combine these multiple FDBs we expose new caps to allow
this:
- Set root flow table which isn't native.
- Set FDB a different selection mode when in LAG mode.
Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Reviewed-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'drivers/net/ethernet/intel/ice/ice_lib.c')
0 files changed, 0 insertions, 0 deletions