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authorRoger Quadros <rogerq@ti.com>2016-02-19 11:01:02 +0200
committerRoger Quadros <rogerq@ti.com>2016-04-15 11:55:06 +0300
commitb2bac25a4d298309bb4b2649bb1107ddaa287c47 (patch)
treef8bf795b115860f570f179f3ee65ffa6b992a0a8 /drivers/mtd/nand/omap2.c
parent210325f0f4eb531f83ffb0b0f95612e2a8063983 (diff)
memory: omap-gpmc: Support WAIT pin edge interrupts
OMAPs can have 2 to 4 WAITPINs that can be used as edge triggered interrupts if not used for memory wait state insertion. Support these interrupts via the gpmc IRQ domain. The gpmc IRQ domain interrupt map is: 0 - NAND_fifoevent 1 - NAND_termcount 2 - GPMC_WAIT0 edge 3 - GPMC_WAIT1 edge, and so on Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'drivers/mtd/nand/omap2.c')
0 files changed, 0 insertions, 0 deletions