diff options
| author | Dmitry Torokhov <[email protected]> | 2017-09-04 09:22:54 -0700 | 
|---|---|---|
| committer | Dmitry Torokhov <[email protected]> | 2017-09-04 09:22:54 -0700 | 
| commit | a6cbfa1e6d38c4b3ab0ce7e3aea4bb4e744f24b8 (patch) | |
| tree | 8960e571a398b5d32e72bdb9c89ce965daa870ab /drivers/misc/cxl/fault.c | |
| parent | f5308d1b83eba20e69df5e0926ba7257c8dd9074 (diff) | |
| parent | 08d6ac9ee5fedd82040bc878705981b67a116a3f (diff) | |
Merge branch 'next' into for-linus
Prepare input updates for 4.14 merge window.
Diffstat (limited to 'drivers/misc/cxl/fault.c')
| -rw-r--r-- | drivers/misc/cxl/fault.c | 23 | 
1 files changed, 15 insertions, 8 deletions
diff --git a/drivers/misc/cxl/fault.c b/drivers/misc/cxl/fault.c index 5344448f514e..c79e39bad7a4 100644 --- a/drivers/misc/cxl/fault.c +++ b/drivers/misc/cxl/fault.c @@ -187,7 +187,7 @@ static struct mm_struct *get_mem_context(struct cxl_context *ctx)  static bool cxl_is_segment_miss(struct cxl_context *ctx, u64 dsisr)  { -	if ((cxl_is_psl8(ctx->afu)) && (dsisr & CXL_PSL_DSISR_An_DS)) +	if ((cxl_is_power8() && (dsisr & CXL_PSL_DSISR_An_DS)))  		return true;  	return false; @@ -195,16 +195,23 @@ static bool cxl_is_segment_miss(struct cxl_context *ctx, u64 dsisr)  static bool cxl_is_page_fault(struct cxl_context *ctx, u64 dsisr)  { -	if ((cxl_is_psl8(ctx->afu)) && (dsisr & CXL_PSL_DSISR_An_DM)) -		return true; +	u64 crs; /* Translation Checkout Response Status */ -	if ((cxl_is_psl9(ctx->afu)) && -	   ((dsisr & CXL_PSL9_DSISR_An_CO_MASK) & -		(CXL_PSL9_DSISR_An_PF_SLR | CXL_PSL9_DSISR_An_PF_RGC | -		 CXL_PSL9_DSISR_An_PF_RGP | CXL_PSL9_DSISR_An_PF_HRH | -		 CXL_PSL9_DSISR_An_PF_STEG))) +	if ((cxl_is_power8()) && (dsisr & CXL_PSL_DSISR_An_DM))  		return true; +	if (cxl_is_power9()) { +		crs = (dsisr & CXL_PSL9_DSISR_An_CO_MASK); +		if ((crs == CXL_PSL9_DSISR_An_PF_SLR) || +		    (crs == CXL_PSL9_DSISR_An_PF_RGC) || +		    (crs == CXL_PSL9_DSISR_An_PF_RGP) || +		    (crs == CXL_PSL9_DSISR_An_PF_HRH) || +		    (crs == CXL_PSL9_DSISR_An_PF_STEG) || +		    (crs == CXL_PSL9_DSISR_An_URTCH)) { +			return true; +		} +	} +  	return false;  }  |