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| author | Anup Patel <anup.patel@wdc.com> | 2020-02-02 16:32:02 +0530 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-02-18 10:34:04 -0800 |
| commit | 6a1ce99dc4bde564e4a072936f9d41f4a439140e (patch) | |
| tree | b3276a7e054211e946d56879c7245412ebfca492 /drivers/iio/trigger/stm32-timer-trigger.c | |
| parent | c68a9032299e837b56d356de9250c93094f7e0e3 (diff) | |
RISC-V: Don't enable all interrupts in trap_init()
Historically, we have been enabling all interrupts for each
HART in trap_init(). Ideally, we should only enable M-mode
interrupts for M-mode kernel and S-mode interrupts for S-mode
kernel in trap_init().
Currently, we get suprious S-mode interrupts on Kendryte K210
board running M-mode NO-MMU kernel because we are enabling all
interrupts in trap_init(). To fix this, we only enable software
and external interrupt in trap_init(). In future, trap_init()
will only enable software interrupt and PLIC driver will enable
external interrupt using CPU notifiers.
Fixes: a4c3733d32a7 ("riscv: abstract out CSR names for supervisor vs machine mode")
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Palmer Dabbelt <palmerdabbelt@google.com> [QMEU virt machine with SMP]
[Palmer: Move the Fixes up to a newer commit]
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'drivers/iio/trigger/stm32-timer-trigger.c')
0 files changed, 0 insertions, 0 deletions