diff options
| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2021-01-29 10:29:39 -0800 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2021-02-01 05:44:34 -0800 |
| commit | a7ffb8154d698cdcf5cad3f859f2cd7efb73ae82 (patch) | |
| tree | 0cf1adfb8d1e206fb2e52b1ed3fd45776ea2ff8e /drivers/gpu/drm | |
| parent | b4cd8dd367ad1ec0e1aba45a59800361140b458a (diff) | |
drm/i915/adl_s: Add power wells
TGL power wells can be re-used for ADL-S with the exception of the fake
power well for TC_COLD, just like DG-1.
BSpec: 53597
Bspec: 49231
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210129182945.217078-3-aditya.swarup@intel.com
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_power.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index bb04b502a442..2f35a217f95a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4689,7 +4689,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) * The enabling order will be from lower to higher indexed wells, * the disabling order is reversed. */ - if (IS_DG1(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { err = set_power_wells_mask(power_domains, tgl_power_wells, BIT_ULL(TGL_DISP_PW_TC_COLD_OFF)); } else if (IS_ROCKETLAKE(dev_priv)) { |