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authorRodrigo Vivi <rodrigo.vivi@intel.com>2023-07-26 17:03:52 -0400
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-21 11:39:15 -0500
commit063e09af6e1d9a4f26cdd0eb896c19526cb0afd3 (patch)
tree45f5d92bd4ef69d512ce6d6fef66f5f608f6015f /drivers/gpu/drm/xe/xe_pcode.c
parentf83a30f466ebbd56355b1f65ec9bcd5087840ffc (diff)
drm/xe: Invert mask and val in xe_mmio_wait32.
The order: 'offset, mask, val'; is more common in other drivers and in special in i915, where any dev could copy a sequence and end up with unexpected behavior. Done with coccinelle: @rule1@ expression gt, reg, val, mask, timeout, out, atomic; @@ - xe_mmio_wait32(gt, reg, val, mask, timeout, out, atomic) + xe_mmio_wait32(gt, reg, mask, val, timeout, out, atomic) spatch -sp_file mmio.cocci *.c *.h compat-i915-headers/intel_uncore.h \ --in-place v2: Rebased after changes on xe_guc_mcr usage of xe_mmio_wait32. Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_pcode.c')
-rw-r--r--drivers/gpu/drm/xe/xe_pcode.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
index e3ab1d3a367f..7f1bf2297f51 100644
--- a/drivers/gpu/drm/xe/xe_pcode.c
+++ b/drivers/gpu/drm/xe/xe_pcode.c
@@ -68,7 +68,7 @@ static int pcode_mailbox_rw(struct xe_gt *gt, u32 mbox, u32 *data0, u32 *data1,
xe_mmio_write32(gt, PCODE_DATA1, data1 ? *data1 : 0);
xe_mmio_write32(gt, PCODE_MAILBOX, PCODE_READY | mbox);
- err = xe_mmio_wait32(gt, PCODE_MAILBOX, 0, PCODE_READY,
+ err = xe_mmio_wait32(gt, PCODE_MAILBOX, PCODE_READY, 0,
timeout_ms * 1000, NULL, atomic);
if (err)
return err;