diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2015-11-08 12:16:40 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2016-01-11 11:17:40 +1000 |
| commit | 845f27253c34204bb33acb7dfeeb9f7163443efb (patch) | |
| tree | 034d6a219d38391add8ec01d8c273b28540d91c7 /drivers/gpu/drm/nouveau/include | |
| parent | 75445a4d6423e7f742fcfe2b06eee3ce9c7de4c0 (diff) | |
drm/nouveau/nvif: split out ctxdma interface definitions
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/include')
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/cl0002.h | 66 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/class.h | 74 |
2 files changed, 69 insertions, 71 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl0002.h b/drivers/gpu/drm/nouveau/include/nvif/cl0002.h new file mode 100644 index 000000000000..6d72ed38da32 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl0002.h @@ -0,0 +1,66 @@ +#ifndef __NVIF_CL0002_H__ +#define __NVIF_CL0002_H__ + +struct nv_dma_v0 { + __u8 version; +#define NV_DMA_V0_TARGET_VM 0x00 +#define NV_DMA_V0_TARGET_VRAM 0x01 +#define NV_DMA_V0_TARGET_PCI 0x02 +#define NV_DMA_V0_TARGET_PCI_US 0x03 +#define NV_DMA_V0_TARGET_AGP 0x04 + __u8 target; +#define NV_DMA_V0_ACCESS_VM 0x00 +#define NV_DMA_V0_ACCESS_RD 0x01 +#define NV_DMA_V0_ACCESS_WR 0x02 +#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) + __u8 access; + __u8 pad03[5]; + __u64 start; + __u64 limit; + /* ... chipset-specific class data */ +}; + +struct nv50_dma_v0 { + __u8 version; +#define NV50_DMA_V0_PRIV_VM 0x00 +#define NV50_DMA_V0_PRIV_US 0x01 +#define NV50_DMA_V0_PRIV__S 0x02 + __u8 priv; +#define NV50_DMA_V0_PART_VM 0x00 +#define NV50_DMA_V0_PART_256 0x01 +#define NV50_DMA_V0_PART_1KB 0x02 + __u8 part; +#define NV50_DMA_V0_COMP_NONE 0x00 +#define NV50_DMA_V0_COMP_1 0x01 +#define NV50_DMA_V0_COMP_2 0x02 +#define NV50_DMA_V0_COMP_VM 0x03 + __u8 comp; +#define NV50_DMA_V0_KIND_PITCH 0x00 +#define NV50_DMA_V0_KIND_VM 0x7f + __u8 kind; + __u8 pad05[3]; +}; + +struct gf100_dma_v0 { + __u8 version; +#define GF100_DMA_V0_PRIV_VM 0x00 +#define GF100_DMA_V0_PRIV_US 0x01 +#define GF100_DMA_V0_PRIV__S 0x02 + __u8 priv; +#define GF100_DMA_V0_KIND_PITCH 0x00 +#define GF100_DMA_V0_KIND_VM 0xff + __u8 kind; + __u8 pad03[5]; +}; + +struct gf119_dma_v0 { + __u8 version; +#define GF119_DMA_V0_PAGE_LP 0x00 +#define GF119_DMA_V0_PAGE_SP 0x01 + __u8 page; +#define GF119_DMA_V0_KIND_PITCH 0x00 +#define GF119_DMA_V0_KIND_VM 0xff + __u8 kind; + __u8 pad03[5]; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 3392b7703cc1..c08db4ccfb2a 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -13,9 +13,9 @@ /* the below match nvidia-assigned (either in hw, or sw) class numbers */ #define NV_DEVICE 0x00000080 -#define NV_DMA_FROM_MEMORY 0x00000002 -#define NV_DMA_TO_MEMORY 0x00000003 -#define NV_DMA_IN_MEMORY 0x0000003d +#define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002 +#define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003 +#define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d #define FERMI_TWOD_A 0x0000902d @@ -198,72 +198,4 @@ struct nv_device_time_v0 { __u8 pad01[7]; __u64 time; }; - - -/******************************************************************************* - * context dma - ******************************************************************************/ - -struct nv_dma_v0 { - __u8 version; -#define NV_DMA_V0_TARGET_VM 0x00 -#define NV_DMA_V0_TARGET_VRAM 0x01 -#define NV_DMA_V0_TARGET_PCI 0x02 -#define NV_DMA_V0_TARGET_PCI_US 0x03 -#define NV_DMA_V0_TARGET_AGP 0x04 - __u8 target; -#define NV_DMA_V0_ACCESS_VM 0x00 -#define NV_DMA_V0_ACCESS_RD 0x01 -#define NV_DMA_V0_ACCESS_WR 0x02 -#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) - __u8 access; - __u8 pad03[5]; - __u64 start; - __u64 limit; - /* ... chipset-specific class data */ -}; - -struct nv50_dma_v0 { - __u8 version; -#define NV50_DMA_V0_PRIV_VM 0x00 -#define NV50_DMA_V0_PRIV_US 0x01 -#define NV50_DMA_V0_PRIV__S 0x02 - __u8 priv; -#define NV50_DMA_V0_PART_VM 0x00 -#define NV50_DMA_V0_PART_256 0x01 -#define NV50_DMA_V0_PART_1KB 0x02 - __u8 part; -#define NV50_DMA_V0_COMP_NONE 0x00 -#define NV50_DMA_V0_COMP_1 0x01 -#define NV50_DMA_V0_COMP_2 0x02 -#define NV50_DMA_V0_COMP_VM 0x03 - __u8 comp; -#define NV50_DMA_V0_KIND_PITCH 0x00 -#define NV50_DMA_V0_KIND_VM 0x7f - __u8 kind; - __u8 pad05[3]; -}; - -struct gf100_dma_v0 { - __u8 version; -#define GF100_DMA_V0_PRIV_VM 0x00 -#define GF100_DMA_V0_PRIV_US 0x01 -#define GF100_DMA_V0_PRIV__S 0x02 - __u8 priv; -#define GF100_DMA_V0_KIND_PITCH 0x00 -#define GF100_DMA_V0_KIND_VM 0xff - __u8 kind; - __u8 pad03[5]; -}; - -struct gf119_dma_v0 { - __u8 version; -#define GF119_DMA_V0_PAGE_LP 0x00 -#define GF119_DMA_V0_PAGE_SP 0x01 - __u8 page; -#define GF119_DMA_V0_KIND_PITCH 0x00 -#define GF119_DMA_V0_KIND_VM 0xff - __u8 kind; - __u8 pad03[5]; -}; #endif |