diff options
author | Dave Airlie <airlied@redhat.com> | 2022-05-11 12:40:47 +1000 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2022-05-11 12:40:47 +1000 |
commit | f83493f7d34da258310ecd3d07f0cc78f884c954 (patch) | |
tree | 5b0d034a505dc8a0f42a16fe17407e443afae32d /drivers/gpu/drm/msm/msm_ringbuffer.c | |
parent | d53b8e19c24bab37f72a2fc4b61d6f4d77b84ab4 (diff) | |
parent | 24df12013853ac59c52cc726e9cbe51e38d09eda (diff) |
Merge tag 'drm-msm-next-2022-05-09' of https://gitlab.freedesktop.org/drm/msm into drm-next
- Fourcc modifier for tiled but not compressed layouts
- Support for userspace allocated IOVA (GPU virtual address)
- Devfreq clamp_to_idle fix
- DPU: DSC (Display Stream Compression) support
- DPU: inline rotation support on SC7280
- DPU: update DP timings to follow vendor recommendations
- DP, DPU: add support for wide bus (on newer chipsets)
- DP: eDP support
- Merge DPU1 and MDP5 MDSS driver, make dpu/mdp device the master
component
- MDSS: optionally reset the IP block at the bootup to drop
bootloader state
- Properly register and unregister internal bridges in the DRM framework
- Complete DPU IRQ cleanup
- DP: conversion to use drm_bridge and drm_bridge_connector
- eDP: drop old eDP parts again
- DPU: writeback support
- Misc small fixes
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvJCr_1D8d0dgmyQC5HD4gmXeZw=bFV_CNCfceZbpMxRw@mail.gmail.com
Diffstat (limited to 'drivers/gpu/drm/msm/msm_ringbuffer.c')
-rw-r--r-- | drivers/gpu/drm/msm/msm_ringbuffer.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c index 367a6aaa3a20..43066320ff8c 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.c +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c @@ -14,9 +14,20 @@ module_param(num_hw_submissions, uint, 0600); static struct dma_fence *msm_job_run(struct drm_sched_job *job) { struct msm_gem_submit *submit = to_msm_submit(job); + struct msm_fence_context *fctx = submit->ring->fctx; struct msm_gpu *gpu = submit->gpu; + int i; - submit->hw_fence = msm_fence_alloc(submit->ring->fctx); + submit->hw_fence = msm_fence_alloc(fctx); + + for (i = 0; i < submit->nr_bos; i++) { + struct drm_gem_object *obj = &submit->bos[i].obj->base; + + msm_gem_lock(obj); + msm_gem_unpin_vma_fenced(submit->bos[i].vma, fctx); + submit->bos[i].flags &= ~BO_PINNED; + msm_gem_unlock(obj); + } pm_runtime_get_sync(&gpu->pdev->dev); @@ -40,7 +51,7 @@ static void msm_job_free(struct drm_sched_job *job) msm_gem_submit_put(submit); } -const struct drm_sched_backend_ops msm_sched_ops = { +static const struct drm_sched_backend_ops msm_sched_ops = { .run_job = msm_job_run, .free_job = msm_job_free }; |