diff options
| author | Jiri Vanek <[email protected]> | 2022-06-16 00:22:21 +0200 |
|---|---|---|
| committer | Robert Foss <[email protected]> | 2022-06-20 21:34:21 +0200 |
| commit | 993a87917c2af59efb0ee1ce43c878ca8790ba1c (patch) | |
| tree | f18eb6f7b5b2fcef040bd6d23a9084a1c42c2770 /drivers/gpu/drm/logicvc/logicvc_layer.c | |
| parent | 89fc846675537f9f6ef62271e9d60556c873d65e (diff) | |
drm/bridge/tc358775: Fix DSI clock division for vsync delay calculation
Use the same PCLK divide option (divide DSI clock to generate pixel clock)
which is set to LVDS Configuration Register (LVCFG) also for a VSync delay
calculation. Without this change an auxiliary variable could underflow
during the calculation for some dual-link LVDS panels and then calculated
VSync delay is wrong. This leads to a shifted picture on a panel.
Tested-by: Jiri Vanek <[email protected]>
Signed-off-by: Jiri Vanek <[email protected]>
Reviewed-by: Vinay Simha BN <[email protected]>
Signed-off-by: Robert Foss <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/logicvc/logicvc_layer.c')
0 files changed, 0 insertions, 0 deletions